Szczegóły publikacji
Opis bibliograficzny
Design of the charge-sampling multiplying PLL in CMOS 40 nm / Jakub Zając, Piotr KMON // W: MIXDES 2025 [Dokument elektroniczny] : 32nd international conference on Mixed Design of integrated circuits and systems : 26-27 June 2025, Szczecin, Poland / ed. by Wojciech Tylman. — Wersja do Windows. — Dane tekstowe. — Łódź : Lodz University of Technology ; IEEE, cop. 2025. — e-ISBN: 978-83-63578-27-5. — S. 98–102. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 102. — Publikacja dostępna online od: 2025-07-30
Autorzy (2)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 161039 |
|---|---|
| Data dodania do BaDAP | 2025-07-21 |
| Tekst źródłowy | URL |
| DOI | 10.23919/MIXDES66264.2025.11092179 |
| Rok publikacji | 2025 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawcy | Institute of Electrical and Electronics Engineers (IEEE), Politechnika Łódzka |
Abstract
This paper presents the design of the Charge Sampling Phase-Locked Loop working on 11 GHz with rms jitter less than 100 fs. The presented PLL works with the 100 MHz reference source and its main advantage is a phase detector PD, working in charge domain, allowing to minimize power consumption while simultaneously keeping the high gain of the phase difference. To alleviate spur transfer from periodic phase detector to PLL high common mode rejection ratio, CMRR operational transconductance amplifier OTA is used with Common Mode CM amplifier, which tune OTA output level improving frequency range. In addition, the differential input class D/F2 Voltage Controlled Oscillator VCO with one inductor turn is used. The proposed circuit is designed in the CMOS 40 nm process, is supplied from two supply sources 1.1 V and 0.6 V and consumes about 5 mW of power.
