Szczegóły publikacji
Opis bibliograficzny
Mismatch analysis of DTCs with an improved BIST-TDC in 28-nm CMOS / Peng Chen, Jun Yin, Feifei Zhang, Pui-In Mak, Rui P. Martins, Robert Bogdan STASZEWSKI // IEEE Transactions on Circuits and Systems. I, Regular Papers ; ISSN 1549-8328. — 2022 — vol. 69 no. 1, s. 196–206. — Bibliogr. s. 204–205, Abstr. — Publikacja dostępna online od: 2021-08-27. — R. B. Staszewski - afiliacja: University of Science and Technology, Krakow; dod. afiliacja: University College Dublin, Ireland
Autorzy (6)
- Chen Peng
- Yin Jun
- Zhang Feifei
- Mak Pui-In
- Martins Rui P.
- AGHStaszewski Bogdan
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 138983 |
|---|---|
| Data dodania do BaDAP | 2022-02-09 |
| Tekst źródłowy | URL |
| DOI | 10.1109/TCSI.2021.3105451 |
| Rok publikacji | 2022 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | IEEE Transactions on Circuits and Systems, I, Regular Papers |
Abstract
Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the ΔΣ loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks’ nonlinearities.
