Szczegóły publikacji

Opis bibliograficzny

Nonlinearity-induced spur analysis in fractional-N synthesizers with $\Delta\Sigma$ quantization cancellation / Yizhe Hu, Weichen Tao, Robert Bogdan STASZEWSKI // IEEE Open Journal of the Solid-State Circuits Society [Dokument elektroniczny] — Czasopismo elektroniczne ; ISSN 2644-1349. — 2024 — vol. 4, s. 226–237. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 235–237, Abstr. — Publikacja dostępna online od: 2024-10-08. — R. B. Staszewski - dod. afiliacja: University College Dublin, Ireland

Autorzy (3)

Słowa kluczowe

DSMall digital phase locked loopfractional-Nintegral nonlinearityINLmmWavespurmillimeter wavesdelta sigma modulatordigital-to-time converterall digital PLLADPLLDTC

Dane bibliometryczne

ID BaDAP163590
Data dodania do BaDAP2025-10-29
Tekst źródłowyURL
DOI10.1109/OJSSCS.2024.3476035
Rok publikacji2024
Typ publikacjiartykuł w czasopiśmie
Otwarty dostęptak
Creative Commons
Czasopismo/seriaIEEE Open Journal of the Solid-State Circuits Society

Abstract

A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7). While fractional-N phase-locked loops (PLLs) and injection-locking techniques with delta–sigma (ΔΣ) quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order ΔΣ modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.

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