Szczegóły publikacji
Opis bibliograficzny
A PLL technique: charge-steering sampling / Weichen Tao, Yuhao Yang, Robert Bogdan STASZEWSKI, Yizhe Hu // IEEE Journal of Solid-State Circuits ; ISSN 0018-9200 . — 2026 — vol. 61 iss. 2, s. 475–490. — Bibliogr. s. 489–490, Abstr. — Publikacja dostępna online od: 2025-05-29. — R. B. Staszewski - dod. afiliacja: University College Dublin, Ireland
Autorzy (4)
- Tao Weichen
- Yang Yuhao
- AGHStaszewski Bogdan
- Hu Yizhe
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 165976 |
|---|---|
| Data dodania do BaDAP | 2026-03-09 |
| Tekst źródłowy | URL |
| DOI | 10.1109/JSSC.2025.3566271 |
| Rok publikacji | 2026 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | IEEE Journal of Solid-State Circuits |
Abstract
This article introduces a charge-steering sampling (CSS) technique for time-error detection (TD), an equivalent of phase detection (PD), in phase-locked loops (PLLs). The CSS mechanism presets the input capacitors of a successive approximation register (SAR) analog-to-digital converter (ADC) to VDD and subsequently discharges them during a reference-triggered pulse through a pseudo-differential MOS pair directly driven by the oscillator. The resulting differential-mode (DM) charge residue, proportional to the time error, is digitized by the ADC to support all-digital PLL (ADPLL) operation. The proposed technique simultaneously achieves high-TD gain for low jitter, the excellent oscillator isolation for reduced reference spur, and multi-bit digital TD output for fast locking, fully leveraging the capabilities of advanced CMOS technology. A digital loop filter (DLF) featuring a dead zone (DZ) in the integral path is introduced to mitigate potential conflicts with the proportional path. To accommodate the short-oscillator period Tosc at millimeter-wave (mm-wave) frequencies, we propose extending the CSS pulsewidth to 1.5Tosc. In addition, a damped-sine waveform model for the CSS current is developed, providing deeper insights into the high-TD gain characteristics. The comprehensive noise analysis of the CSS is conducted using a multirate timestamp model, identifying contributions to the output phase noise (PN). Fabricated in 22-nm CMOS, the 18.8–23.3-GHz CSS-ADPLL prototype achieves 63-fs rms jitter, −52.4-dBc reference spur, and a figure of merit (FoM) of −254 dB, while consuming 9.95-mW total power, with only 1.3 mW allocated to the loop. For an initial frequency error of 200 MHz, the system achieves a locking time of 0.61 µs, benefiting from the combined effects of a counter-based frequency-locked loop (FLL) (0.27 µs) and the multi-bit digital output of the CSS ADPLL (0.34 µs).
