Szczegóły publikacji
Opis bibliograficzny
Frequency-domain adaptive-resolution level-crossing-sampling ADC / Hongying Wang, Filippo Schembari, Robert Bogdan Staszewski, Marek MIŚKOWICZ // W: EBCCSP 2017 [Dokument elektroniczny] : 3th international conference on Event-Based Control, Communication and Signal Processing : May 24–26 2017, Funchal, Madeira, Portugal : proceedings. — Wersja do Windows. — Dane tekstowe. — [USA] : IEEE, cop. 2017. — e-ISBN: 978-1-5386-0915-6. — S. [1–5]. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. [5], Abstr. — Publikacja dostępna online od: 2017-08-31
Autorzy (4)
- Wang Hongying
- Schembari Filippo
- Staszewski Bogdan
- AGHMiśkowicz Marek
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 113244 |
|---|---|
| Data dodania do BaDAP | 2018-04-20 |
| Tekst źródłowy | URL |
| DOI | 10.1109/EBCCSP.2017.8022825 |
| Rok publikacji | 2017 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Institute of Electrical and Electronics Engineers (IEEE) |
| Konferencja | 3rd international conference on Event-Based Control, Communication and Signal Processing |
Abstract
In the framework of the large-scale wireless sensor networks involved in the Internet-of-Things (IoT), analog-to-digital converters (ADCs) must target ever increasing levels of power efficiency and amenability to ultra-scaled CMOS technologies. Digitally intensive architectures and smart conversion algorithms are therefore the fuel of future ultra-low power (ULP) designs. The minimization of the output average bit-rate is an effective way to maximize the system energy efficiency. Level-crossing-sampling (LC) ADCs are a class of converters that addresses such problem. In their conventional implementation, however, they are mainly impaired by analog blocks (i.e. the high-performance comparators), difficult to be designed in deep nanoscale CMOS. This paper describes a highly-digital frequency-domain implementation of a LC ADC, which replaces the analog comparators with an oscillator-based quantizer and simple digital logic. LC is performed in the digital frequency-domain, where the application of adaptive-resolution algorithms to further enhance power efficiency becomes straightforward. Behavioral modeling simulations demonstrate the appropriateness of the proposed topology by comparing it with the conventional designs and by evaluating the impact of the oscillator-based-quantizer nonidealities on the ADC performance.