Szczegóły publikacji
Opis bibliograficzny
An adaptive-resolution quasi-level-crossing-sampling adc based on residue quantization in 28-nm CMOS / Hongying Wang, Filippo Schembari, Marek MIŚKOWICZ, Robert Bogdan Staszewski // IEEE Solid-State Circuits Letters [Dokument elektroniczny]. — Czasopismo elektroniczne ; ISSN 2573-9603. — 2018 — vol. 1 no. 8, s. 178–181. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 181, Abstr.
Autorzy (4)
- Wang Hongying
- Schembari Filippo
- AGHMiśkowicz Marek
- Staszewski Bogdan
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 120609 |
|---|---|
| Data dodania do BaDAP | 2019-03-26 |
| Tekst źródłowy | URL |
| DOI | 10.1109/LSSC.2019.2899723 |
| Rok publikacji | 2018 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | IEEE Solid-State Circuits Letters |
Abstract
We present a digitally intensive adaptive-resolution (AR) quasi-level-crossing-sampling (quasi-LCS) analog-to-digital converter (ADC) for Internet-of-Things wireless networks, where the power consumed in data transmission, processing, and storage can be significantly reduced by minimizing the ADC’s gross output bit-rate. The AR quasi-LCS ADC is implemented as a delta-modulator and adopts a 4-bit asynchronous SAR ADC to quantize the residue voltage signal, thus allowing a straightforward implementation of LCS and AR algorithms in the digital domain, as well as yielding a digital-friendly architecture. Fabricated in 28-nm CMOS, this ADC achieves an SNDR of 53 dB over 1.42 MHz signal bandwidth while consuming 205 μW and an active area of 0.0126mm2.