Szczegóły publikacji
Opis bibliograficzny
Dynamic equalization of logic delays in feedback-based successive approximation TDCs / Jakub SZYDUCZYŃSKI, Dariusz KOŚCIELNIK, Marek MIŚKOWICZ // W: EBCCSP 2017 [Dokument elektroniczny] : 3th international conference on Event-Based Control, Communication and Signal Processing : May 24–26 2017, Funchal, Madeira, Portugal : proceedings. — Wersja do Windows. — Dane tekstowe. — [USA] : IEEE, cop. 2017. — e-ISBN: 978-1-5386-0915-6. — S. [1–6]. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. [6], Abstr.
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 108380 |
|---|---|
| Data dodania do BaDAP | 2017-09-18 |
| DOI | 10.1109/EBCCSP.2017.8022824 |
| Rok publikacji | 2017 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Institute of Electrical and Electronics Engineers (IEEE) |
| Konferencja | 3rd international conference on Event-Based Control, Communication and Signal Processing |
Abstract
The paper is focused on a development of a feedback-based architecture for successive-approximation time-to-digital converter (SA-TDC). The adoption of the feedback-based rather than feedforward architecture for the n-bit SA-TDCs is inspired by the classic successive approximation voltage-to-digital converter and motivated by a possible reduction of the number of time comparators from n to one. Nevertheless, existing developments of the feedback-based SA-TDC are characterized by much longer conversion time than that for feedforward SA-TDCs. In the paper, a concept of the feedback-based SA-TDC with dynamic equalization of logic propagation delays in the feedback loops is presented. The use of this technique allows to maintain the conversion time of the feedback-based SA-TDC the same as for the feedforward SA-TDC with just a single time comparator.
