Szczegóły publikacji
Opis bibliograficzny
Behavioral modelling and optimization of a cyclic feedback-based successive approximation TDC with dynamic delay equalization / J. SZYDUCZYŃSKI, V. Nguyen, F. Schembari, R. B. Staszewski, D. KOŚCIELNIK, M. MIŚKOWICZ // W: EBCCSP 2019 [Dokument elektroniczny] : 5th international conference on Event-Based Control, Communication and Signal Processing : May 27–29, 2019, Vienna, Austria : proceedings. — Wersja do Windows. — Dane tekstowe. — [Piscataway] : Institute of Electrical and Electronics Engineers, cop. 2019. — e-ISBN: 978-1-7281-2322-6. — S. [1–9]. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. [9], Abstr. — Publikacja dostępna online od: 2019-09-16
Autorzy (6)
- AGHSzyduczyński Jakub
- Nguyen V.
- Schembari Filippo
- Staszewski Bogdan
- AGHKościelnik Dariusz
- AGHMiśkowicz Marek
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 125736 |
|---|---|
| Data dodania do BaDAP | 2020-01-17 |
| Tekst źródłowy | URL |
| DOI | 10.1109/EBCCSP.2019.8836859 |
| Rok publikacji | 2019 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Institute of Electrical and Electronics Engineers (IEEE) |
Abstract
This paper investigates the performance of cyclic feedback-based Successive Approximation Time-to-Digital Converter (SA - TDC) with dynamic delay equalization aimed to improve its conversion speed. The converter architecture is studied through numerical and behavioral modelling simulations presenting relevant implementation details and the impact of circuit non-idealities such as devices mismatch and noise. A comprehensive investigation of the dynamic delay equalization technique provides useful insights on the nominal achievable performance (i.e. effective time resolution), as well as circuit implementation guidelines. Furthermore, two novel alternative SA TDC topologies are proposed, targeting superior power efficiency with negligible hardware overhead.
