Szczegóły publikacji
Opis bibliograficzny
Design and analysis of multi-level $n-to-2^{n}$ decoders in CMOS technology / Ireneusz BRZOZOWSKI, Piotr DZIURDZIA, Andrzej KOS // W: ICSES 2014 [Dokument elektroniczny] : International Conference on Signals and Electronic Systems : Poznań, Poland, 11–13 September 2014 : international conference / Faculty of Electronics and Telecommunications. Poznan University of Technology. — Wersja do Windows. — Dane tekstowe. — [Poznan : University of Technology], [2014]. — Dysk Flash. — e-ISBN: 978-1-4799-7009-4. — S. [1–4]. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. [4], Abstr.
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 83830 |
|---|---|
| Data dodania do BaDAP | 2014-09-22 |
| DOI | 10.1109/ICSES.2014.6948709 |
| Rok publikacji | 2014 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Konferencja | International Conference on Signals and Electronic Systems |
Abstract
This paper presents designs and analysis of n-to-2(n)-lines decoders created using fast and efficient method. Thanks to especially designed building blocks a decoder of any size can be built in easy way. Layouts of all needed fundamental blocks were designed in UMC 180 CMOS technology, as standard cells. A few layouts of decoders were designed as one and multi-level structures and their parameters such as energy, time, and area were assessed. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. Thanks to these analyses some interesting and important conclusions are derived.