Szczegóły publikacji
Opis bibliograficzny
Time and energy measuring front-end electronics for long silicon strip detectors readout / R. KŁECZEK, R. SZCZYGIEŁ, P. GRYBOŚ, P. OTFINOWSKI, K. KASIŃSKI // W: 2013 IEEE NSS/MIC [Dokument elektroniczny] : Nuclear Science Symposium & Medical Imaging Conference : October 27 – November 2, Seoul, Korea / guest ed. Yong Choi ; Institute of Electrical and Electronics Engineers. — Wersja do Windows. — Dane tekstowe. — [Piscataway : IEEE], cop. 2013. — 1 dysk optyczny. — e-ISBN: 978-1-4799-3423-2. — S. [1–4]. — Wymagania systemowe: Adobe Reader ; napęd CD-ROM. — Bibliogr. s. [4], Abstr. — W bazie Web of Science wersja drukowana. — ISBN 978-1-4799-0534-8
Autorzy (5)
Dane bibliometryczne
| ID BaDAP | 81326 |
|---|---|
| Data dodania do BaDAP | 2014-05-14 |
| DOI | 10.1109/NSSMIC.2013.6829538 |
| Rok publikacji | 2013 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Konferencja | 60th IEEE Nuclear Science Symposium / Medical Imaging Conference / 20th International Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors |
Abstract
We report on the design of a self-triggered analog front-end readout electronics dedicated for signal detection from double-sided silicon microstrip sensors with capacitance at the order of tens pF (C-DET approximate to 30 pF). The main requirements are: processing input pulses with the average rate of 150 kHz/channel, low power consumption and low noise at the same time. The single channel is built of two different parallel processing chains: the fast and slow. The fast path includes: a fast CR-RC shaper with the peaking time t(p) = 40 ns, a discriminator, a pulse stretcher and a time stamp latch. It is optimized to determine an input charge arrival time with resolution at the order of few ns. The slow path consists of: a slow shaper with the peaking time t(p) = 80 ns, a 5-bit flash ADC and a digital peak detector. This chain is dedicated for accurate energy measurement and it is optimized for low noise level. To protect against false noise-related hits coming from noisy fast processing path when the discrimination threshold is set low, the time-stamp validation circuit is used. Two prototype ASICs were implemented in UMC 180 nm CMOS technology: 8-channel AFE-XYTER and 128-channel STS-XYTER.
