Szczegóły publikacji

Opis bibliograficzny

Energy efficient low-noise multichannel neural amplifier in submicron CMOS process / P. KMON, P. GRYBOŚ // IEEE Transactions on Circuits and Systems. I, Regular Papers ; ISSN 1549-8328. — 2013 — vol. 60 no. 7, s. 1764–1775. — Bibliogr. s. 1774–1775, Abstr.

Autorzy (2)

Słowa kluczowe

submicron processesASICmulichannel recording systemneurobiology experiments

Dane bibliometryczne

ID BaDAP74757
Data dodania do BaDAP2013-09-16
Tekst źródłowyURL
DOI10.1109/TCSI.2012.2230504
Rok publikacji2013
Typ publikacjiartykuł w czasopiśmie
Otwarty dostęptak
Czasopismo/seriaIEEE Transactions on Circuits and Systems, I, Regular Papers

Abstract

This paper presents a low noise low power neural recording amplifier that occupies a very small silicon area and is suitable to integrate with multielectrode arrays in cortical implants. We analyze main problems in neural recording systems processed in modern submicron technologies, i.e., leakage currents, ability to obtain very large and precisely controlled MOS based resistances and spread of the main system parameters from channel to channel. We also introduce methods allowing to mitigate them. Finally, we present methods allowing to calculate optimal channel dimensions of the recording channel's input transistors in order to obtain the lowest Input Referred Noise (IRN) for given power and area requirements. The proposed methodology has been applied in the 8-channel integrated recording ASIC dedicated to the broad range of neurobiology experiments. Each of the recording channels is equipped with the control register that enables to set main channel parameters independently. Thanks to this functionality, the user is capable of setting lower cut-off frequency within the range of 300 mHz-900 Hz. The upper cut-off frequency can be switched either to 30 Hz-290 Hz or 9 kHz, while the voltage gain can be set either to 260 V/V or 1000 V/V. A single recording channel is supplied with 1.8 V and consumes only 11 W of power, while its input referred noise is equal to 4.4 mu V resulting in NEF equal to 4.1.

Publikacje, które mogą Cię zainteresować

artykuł
#138983Data dodania: 9.2.2022
Mismatch analysis of DTCs with an improved BIST-TDC in 28-nm CMOS / Peng Chen, Jun Yin, Feifei Zhang, Pui-In Mak, Rui P. Martins, Robert Bogdan STASZEWSKI // IEEE Transactions on Circuits and Systems. I, Regular Papers ; ISSN 1549-8328. — 2022 — vol. 69 no. 1, s. 196–206. — Bibliogr. s. 204–205, Abstr. — Publikacja dostępna online od: 2021-08-27. — R. B. Staszewski - afiliacja: University of Science and Technology, Krakow; dod. afiliacja: University College Dublin, Ireland
fragment książki
#91015Data dodania: 22.7.2015
Design for the testability of the multichannel neural recording and stimulating integrated circuit / Piotr KMON, Piotr OTFINOWSKI, Paweł GRYBOŚ, Robert SZCZYGIEŁ, Mirosław ŻOŁĄDŹ, Agnieszka LISICKA // W: MIXDES 2015 : mixed design of integrated circuits and systems : Toruń, Poland June 25–27, 2015 : book of abstracts of 22nd international conference / ed. Andrzej Napieralski. — Łódź : Lodz University of Technology. Department of Microelectronics and Computer Science, cop. 2015. — e-ISBN: 978-83-63578-06-0. — S. 85. — Abstr. — Pełny tekst na CD-ROMie. — eISBN 978-83-63578-06-0. — S. 305–308. — Wymagania systemowe: Adobe Reader ; napęd CD-ROM. — Bibliogr. s. 308, Abstr.