Szczegóły publikacji
Opis bibliograficzny
Design of low noise charge amplifier in sub-micron technology for fast shaping time / Paweł GRYBOŚ, Marek IDZIK, Andrzej SKOCZEŃ // Analog Integrated Circuits and Signal Processing ; ISSN 0925-1030. — 2006 — vol. 49 iss. 2, s. 107–114. — Bibliogr. s. 113, Abstr. — Publikacja dostępna online od: 2006-09-19. — International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2005) : Cracow, Poland, June, 2005
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 32222 |
|---|---|
| Data dodania do BaDAP | 2007-03-13 |
| Tekst źródłowy | URL |
| DOI | 10.1007/s10470-006-9292-1 |
| Rok publikacji | 2006 |
| Typ publikacji | referat w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | Analog Integrated Circuits and Signal Processing |
Abstract
A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13 mu m to 0.8 mu m and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width.
