Szczegóły publikacji
Opis bibliograficzny
Development of a TAC-based TDC in 130 nm CMOS technology / Mirosław FIRLEJ, Tomasz FIUTOWSKI, Marek IDZIK, Aleksandra MOLENDA, Jakub MOROŃ, Krzysztof ŚWIENTEK // Journal of Instrumentation [Dokument elektroniczny]. — Czasopismo elektroniczne ; ISSN 1748-0221. — 2025 — vol. 20 iss. 1 art. no. C01013, s. [1], 1–6. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 5–6, Abstr. — Publikacja dostępna online od: 2025-01-14. — A. Molenda - dod. afiliacja: Nimbus Intelligence, Milano, Italy. — Topical Workshop on Electronics for Particle Physics : 30 September – 4 October 2024, Scotland
Autorzy (6)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 158840 |
|---|---|
| Data dodania do BaDAP | 2025-04-15 |
| Tekst źródłowy | URL |
| DOI | 10.1088/1748-0221/20/01/C01013 |
| Rok publikacji | 2025 |
| Typ publikacji | referat w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | Journal of Instrumentation |
Abstract
The design and measurement results of a prototype Time-to-Digital Converter (TDC) fabricated in 130 nm CMOS technology are presented. The TDC architecture with analog interpolators was chosen, which was motivated by previous experience in Analog-to-Digital Converter (ADC) design [1]. The measured time difference between the event and the trigger signal is converted to the amplitude and then digitised by a 10-bit ADC. The TDC prototype is functional and achieved good Differential Non-Linearity (DNL) and jitter (below 1 LSB), slightly dependent of the selected time precision. The obtained Integral Non-Linearity (INL) is significantly higher than simulated and should be still improved. The prototype Application-Specific Integrated Circuit (ASIC) has configurable time resolution from 15 ps to 140 ps, which gives the total possible time measure range from ±9.5 ns to ±70 ns. In this paper the architecture of the developed TDC is described, comprising the implementation of the Time-to-Analog Converter (TAC) and 10-bit ADC. The measurements of the prototype 8 channel TDC ASIC, showing its linearity and timing resolution are also shown. © 2025 The Author(s)
