Szczegóły publikacji
Opis bibliograficzny
Multilevel diode-clamped voltage inverter with a minimized number of transistors / Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie ; wynalazca: STALA Robert. — Int.Cl.: H02M 7/487(2007.01). — European Patent Office. — Opis zgłoszeniowy wynalazku ; EP4362313A1 ; Opubl. 2024-05-01. — Zgłosz. nr EP22213682A z dn. 2022-12-15
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Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 153395 |
|---|---|
| Data dodania do BaDAP | 2024-06-05 |
| Tekst źródłowy | URL |
| Rok publikacji | 2024 |
| Typ publikacji | zgłoszenie patentowe |
| Otwarty dostęp |  |
Abstract
The subject of the invention is a multilevel diode-clamped voltage inverter having a minimized number of transistors, enabling multilevel modulation of output voltage, created by modifying a classic NPC-type inverter.The modification of the three-phase diode-clamped NPC inverter has been implemented by attaching to it an additional system composed of a capacitive divider constituting a serial connection of capacitors C3 and C4, and three legs, each including one controlled bidirectional switch (S13, S14 and S15), that connect a common connection point of the capacitors C3 and C4 to individual phase legs of the NPC inverter.The inverter according to the invention is implemented in four versions. In a first and a second version, the capacitive divider of the additional system replaces one of the capacitors of the input divider of the NPC inverter, and in a third and a fourth version it is connected in parallel to one of the capacitors of the input divider of the NPC inverter.The voltage between the phases of the system, which is the voltage difference of two legs of the system, can take values: Uin, 4Uin/3, Uin/2, Uin/4, 0, - Uin/4, - Uin/2, -4 Uin/3, - Uin, that is, at 9 levels.
