Szczegóły publikacji
Opis bibliograficzny
ASIC wafer test system for the ATLAS Semiconductor Tracker front-end chip / F. Anghinolfi, W. BIAŁAS, [et al.] // IEEE Transactions on Nuclear Science ; ISSN 0018-9499 . — 2002 — vol. 49 no. 3 pt. 2 art. no. PII S0018-9499(20)06127-0, s. 1080–1085. — Bibliogr. s. 1085, Abstr. — IEEE Nuclear Science Symposium : San Diego, California, November 04-10, 2001
Autorzy (22)
- Ahghinolfi F.
- AGHBiałas Wojciech
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 12908 |
|---|---|
| Data dodania do BaDAP | 2003-05-05 |
| Tekst źródłowy | URL |
| DOI | 10.1109/TNS.2002.1039618 |
| Rok publikacji | 2002 |
| Typ publikacji | referat w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | IEEE Transactions on Nuclear Science |
Abstract
An application-specific integrated circuit (ASIC) wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T [1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the Large Hadron Collider. The tester measures values and tolerance ranges of all critical IC parameters, including do parameters, electronic noise, time resolution, clock levels, and clock timing. The tester is controlled by a field-programmable gate array (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and digital-to-analog converter chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pickup noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented.
