Szczegóły publikacji
Opis bibliograficzny
Real-time implementation of adaptive correlation filter tracking for 4K video stream in Zynq UltraScale+ MPSoC / Marcin KOWALCZYK, Dominika PRZEWŁOCKA, Tomasz KRYJAK // W: dasip [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : 16–18 October, 2019, Montréal, Canada. — Wersja do Windows. — Dane tekstowe. — [Piscataway] : IEEE, cop. 2019. — e-ISBN: 978-1-7281-4074-2. — S. 53–58. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 58, Abstr. — Abstrakt pt.: Real-time implementation of adaptive correlation filter tracking for 4K video stream – a demo W: dasip [Dokument elektroniczny] : the conference on Design and Architectures for Signal and Image Processing : TEXPO graduate student research competition : 16–18 October, 2019, Montréal, Canada. — Wersja do Windows. — Dane tekstowe. — [Canada : Polytechnique Montreal], [2019]. — S. [1]. — Wymagania systemowe: Adobe Reader. — Tryb dostępu: https://dasip-conference.org/wp-content/uploads/sites/2/2019/10/DASIP2019_paper_33.pdf [2019-12-02]. — Bibliogr. s. [1]
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 126251 |
|---|---|
| Data dodania do BaDAP | 2019-12-17 |
| Tekst źródłowy | URL |
| DOI | 10.1109/DASIP48288.2019.9049203 |
| Rok publikacji | 2019 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Institute of Electrical and Electronics Engineers (IEEE) |
Abstract
In this paper a hardware-software implementation of adaptive correlation filter tracking for a 3840 × 2160 @ 60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. Correlation filters gained popularity in recent years because of their efficiency and good results in the VOT (Visual Object Tracking) challenge. An implementation of the MOSSE (Minimum Output Sum of Squared Error) algorithm is presented. It utilizes 2-dimensional FFT for computing correlation and updates filter coefficients in every frame. The initial filter coefficients are computed on the ARM processor in the PS (Processing System), while all other operations are preformed in PL (Programmable Logic). The presented architecture was described with the use of Verilog hardware description language.
