Szczegóły publikacji
Opis bibliograficzny
Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale+ MPSoC / Marcin KOWALCZYK, Dominika PRZEWŁOCKA, Tomasz KRYJAK // W: dasip [Dokument elektroniczny] : the 2018 conference on Design & Architectures for Signal & Image Processing : Porto, Portugal, October 10–12, 2018. — Wersja do Windows. — Dane tekstowe. — [Piscataway] : IEEE, cop. 2018. — e-ISBN: 978-1-5386-8237-1. — S. 37–42. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 42, Abstr. — Rozszerzony abstrakt: Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale+ MPSoC – a demo / Marcin KOWALCZYK, Dominika PRZEWŁOCKA, Tomasz KRYJAK // dasip 2018 [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : October 10–12 2018, Porto, Portugal. — Wersja do Windows. — Dane tekstowe. — [Porto : s. n.], [2018]. — S. [1–2]. — Wymagania systemowe: Adobe Reader. — Tryb dostępu: https://web.fe.up.pt/ specs/events/dasip2018/files/paper_46.pdf [2018-11-28]. — Bibliogr. s. [2], Abstr.
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 119438 |
|---|---|
| Data dodania do BaDAP | 2019-02-05 |
| Tekst źródłowy | URL |
| DOI | 10.1109/DASIP.2018.8597105 |
| Rok publikacji | 2018 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Institute of Electrical and Electronics Engineers (IEEE) |
| Konferencja | Conference on Design and Architectures for Signal and Image Processing |
Abstract
In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840×2160 @60 FPS video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: simple averaging (box filter), Gaussian filter, edge detection using the Sobel and Canny methods, median filter and morphological erosion and dilation operations. The scheme for implementing contextual based operations for a video stream in the format of 2 and 4 pixels per clock and challenges related to the pipelined implementation of processing such data are described. Also the use of logic resources and energy efficiency of modules described in the Verilog hardware description language and using the High Level Synthesis tools (Vivado HLS, SDSoC and xfOpenCV library) are compared. All designed modules support real-time processing of a 4K@60 FPS video stream.
