Szczegóły publikacji
Opis bibliograficzny
A 0.0046 $mm^{2}$ low-distortion CMOS neural preamplifier for large-scale neuroelectronic interfaces / Beata TRZPIL-JURGIELEWICZ, Władysław DĄBROWSKI, Paweł HOTTOWY // W: NER'19 : 2019 9th international IEEE/EMBS conference on Neural Engineering (NER) : 20-23 March 2019, San Francisco, California / IEEE. — New York : IEEE, [2019]. — (International IEEE EMBS Conference on Neural Engineering ; ISSN 1948-3546). — ISBN: 978-1-5386-7921-0. — S. 698-701. — Bibliogr. s. 701, Abstr.
Autorzy (3)
Dane bibliometryczne
| ID BaDAP | 123111 |
|---|---|
| Data dodania do BaDAP | 2019-07-29 |
| Tekst źródłowy | URL |
| DOI | 10.1109/NER.2019.8716992 |
| Rok publikacji | 2019 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Institute of Electrical and Electronics Engineers (IEEE) |
| Konferencja | 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER) |
| Czasopismo/seria | International IEEE EMBS Conference on Neural Engineering |
Abstract
We present a design and analysis of nonlinear distortions for low-area integrated neural preamplifier with pseudoresistor-based AC coupling. We evaluate the distortions as a function of frequency, signal amplitude and sizing of the pseudoresistors. We describe a preamplifier design in 0.18 mu m SOI CMOS technology with Total Harmonic Distortions (THD) below 1% in the full range of frequencies and amplitudes of extracellular neural signals. The circuit noise is 5.82 mu V rms in the Local Field Potential (LFP) frequency range (1-300 Hz) and 4.45 mu V rms in the action potential (AP) range (300 Hz -5 kHz). The preamplifier occupies silicon area of 0.0046 mm(2) and is suitable for recording systems with > 10,000 channels per cm(2) of the chip area, providing high-fidelity amplification for large-scale neural interfaces.
