Szczegóły publikacji
Opis bibliograficzny
A successive approximation time-to-digital converter with single set of delay lines for time interval measurements / Jakub SZYDUCZYŃSKI, Dariusz KOŚCIELNIK, Marek MIŚKOWICZ // Sensors [Dokument elektroniczny]. — Czasopismo elektroniczne ; ISSN 1424-8220. — 2019 — vol. 19 iss. 5 art. no. 1109, s. 1–27. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 25–27, Abstr. — Publikacja dostępna online od: 2019-03-05
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 120578 |
|---|---|
| Data dodania do BaDAP | 2019-03-18 |
| Tekst źródłowy | URL |
| DOI | 10.3390/s19051109 |
| Rok publikacji | 2019 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | Sensors |
Abstract
The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs-Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on successive approximation TDCs (SA-TDCs) on the one hand, and to make the contribution to optimization of SA-TDC design on the other. The proposed design optimization consists essentially in reduction of circuit complexity and die area, as well as in improving converter performance. The main paper contribution is the concept of reducing SA-TDC complexity by removing one of two sets of delay lines in the feedforward architecture at the price of simple output decoding. For 12 bits of resolution, the complexity reduction is close to 50%. Furthermore, the paper presents the implementation of 8-bit SA-TDC in 180 nm CMOS technology with a quantization step 25 ps obtained by asymmetrical design of pair of inverters and symmetrized multiplexer control.
