Szczegóły publikacji
Opis bibliograficzny
Optimized design of successive approximation time-to-digital converter with single set of delay lines / Dariusz KOŚCIELNIK, Jakub SZYDUCZYŃSKI, Dominik RZEPKA, Wojciech ANDRYSIEWICZ, Marek MIŚKOWICZ // W: EBCCSP 2016 [Dokument elektroniczny] : [second] international conference on Event-Based Control, Communication and Signal Processing : 13–15 June 2016, Krakow, Poland. — Wersja do Windows. — Dane tekstowe. — [Piscataway] : Institute of Electrical and Electronics Engineers, cop. 2016. — Dysk Flash. — W bazie Web of Science ISBN: 978-1-5090-4196-1. — e-ISBN: 978-1-5090-4195-4. — S. [1–8]. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. [8], Abstr. — Dostęp również online: http://wbg2.bg.agh.edu.pl/stamp/stamp.jsp?arnumber=7605284
Autorzy (5)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 102385 |
|---|---|
| Data dodania do BaDAP | 2016-12-21 |
| DOI | 10.1109/EBCCSP.2016.7605284 |
| Rok publikacji | 2016 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Konferencja | 2nd International Conference on Event-Based Control, Communication, and Signal Processing |
Abstract
The paper addresses the problems of design of picosecond resolution time-to-digital converter based on successive approximation (SA-TDC). The principle of the conversion process in SA-TDC consists in successive delaying the events defining a start and a stop of the input time interval by the use of binary-weighted delays. The paper is focused on optimization of particular components of the SA-TDC architecture with a single set of delay lines in order to reduce differential (DNL) and integral (INL) nonlinearities. In particular, the paper contribution is an improvement of time resolution of the converter from 25 ps to 12.5 ps (i.e., by one extra bit) in 180 nm CMOS technology through enhancements of design of circuit components which results in a reduction of conversion errors.
