Szczegóły publikacji
Opis bibliograficzny
Testing multistage gain and offset trimming in a single photon counting IC with a charge sharing elimination algorithm / A. KRZYŻANOWSKA, P. GRYBOŚ, R. SZCZYGIEŁ, P. MAJ // Journal of Instrumentation [Dokument elektroniczny]. — Czasopismo elektroniczne ; ISSN 1748-0221. — 2015 — vol. 10 poz. C12003, s. [1–2], 1–8. — Bibliogr. s. 8, Abstr. — Publikacja dostępna online od: 2015-12-01. — 17th international workshop on Radiation imaging detectors : 28 June – 2 July 2015, Hamburg, Germany
Autorzy (4)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 94552 |
|---|---|
| Data dodania do BaDAP | 2015-12-04 |
| Tekst źródłowy | URL |
| DOI | 10.1088/1748-0221/10/C12003 |
| Rok publikacji | 2015 |
| Typ publikacji | referat w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | Journal of Instrumentation |
Abstract
Designing a hybrid pixel detector readout electronics operating in a single photon counting mode is a very challenging process, where many main parameters are optimized in parallel (e.g. gain, noise, and threshold dispersion). Additional requirements for a smaller pixel size with extended functionality push designers to use new deep sub-micron technologies. Minimizing the channel size is possible, however, with a decreased pixel size, the charge sharing effect becomes a more important issue. To overcome this problem, we designed an integrated circuit prototype produced in CMOS 40 nm technology, which has an extended functionality of a single pixel. A C8P1 algorithm for the charge sharing effect compensation was implemented. In the algorithm’s first stage the charge is rebuilt in a signal rebuilt hub fed by the CSA (charge sensitive amplifier) outputs from four neighbouring pixels. Then, the pixel with the biggest amount of charge is chosen, after a comparison with all the adjacent ones. In order to process the data in such a complicated way, a certain architecture of a single channel was proposed, which allows for: • processing the signal with the possibility of total charge reconstruction (by connecting with the adjacent pixels), • a comparison of certain pixel amplitude to its 8 neighbours, • the extended testability of each block inside the channel to measure CSA gain dispersion, shaper gain dispersion, threshold dispersion (including the simultaneous generation of different pulse amplitudes from different pixels), • trimming all the necessary blocks for proper operation. We present a solution for multistage gain and offset trimming implemented in the IC prototype. It allows for minimization of the total charge extraction errors, minimization of threshold dispersion in the pixel matrix and minimization of errors of comparison of certain pixel pulse amplitudes with all its neighbours. The detailed architecture of a single channel is presented together with experimental results and an algorithm for proper gain and offset trimming for better uniformity of the pixel matrix.
