Szczegóły publikacji
Opis bibliograficzny
Status of the photomultiplier-based FlashCam camera for the Cherenkov Telescope Array / G. Pühlhofer, [et al.], J. KASPEREK, [et al.], P. J. RAJDA, [et al.], W. Romaszkan, M. Rupiński, [et al.], K. Winiarski, [et al.] // W: Ground-based and airborne telescopes V [Dokument elektroniczny] : 22–27 June 2014, Montréal, Canada / eds. Larry M. Stepp, Roberto Gilmozzi, Helen J. Hall. — Wersja do Windows. — Dane tekstowe. — Bellingham : SPIE, cop. 2014. — (Proceedings of SPIE / The International Society for Optical Engineering ; ISSN 0277-786X ; vol. 9145). — ISBN: 9780819496133. — S. 1–10. — Tryb dostępu: http://proceedings.spiedigitallibrary.org/proceeding.aspx?art... [2015-01-09]. — Bibliogr. s. 10, Abstr. — Tekst dostępny po zalogowaniu
Autorzy (30)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 86968 |
|---|---|
| Data dodania do BaDAP | 2015-02-11 |
| DOI | 10.1117/12.2056837 |
| Rok publikacji | 2014 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Konferencja | Conference on Ground-Based and Airborne Telescopes V |
| Czasopismo/seria | Proceedings of SPIE / The International Society for Optical Engineering |
Abstract
The FlashCam project is preparing a camera prototype around a fully digital FADC-based readout system, for the medium sized telescopes (MST) of the Cherenkov Telescope Array (CTA). The FlashCam design is the first fully digital readout system for Cherenkov cameras, based on commercial FADCs and FPGAs as key components for digitization and triggering, and a high performance camera server as back end. It provides the option to easily implement different types of trigger algorithms as well as digitization and readout scenarios using identical hardware, by simply changing the firmware on the FPGAs. The readout of the front end modules into the camera server is Ethernet-based using standard Ethernet switches and a custom, raw Ethernet protocol. In the current implementation of the system, data transfer and back end processing rates of 3.8 GB/s and 2.4 GB/s have been achieved, respectively. Together with the dead-time-free front end event buffering on the FPGAs, this permits the cameras to operate at trigger rates of up to several ten kHz. In the horizontal architecture of FlashCam, the photon detector plane (PDP), consisting of photon detectors, preamplifiers, high voltage-, control-, and monitoring systems, is a self-contained unit, mechanically detached from the front end modules. It interfaces to the digital readout system via analogue signal transmission. The horizontal integration of FlashCam is expected not only to be more cost efficient, it also allows PDPs with different types of photon detectors to be adapted to the FlashCam readout system. By now, a 144-pixel "mini-camera" setup, fully equipped with photomultipliers, PDP electronics, and digitization/trigger electronics, has been realized and extensively tested. Preparations for a fulll-scale, 1764 pixel camera mechanics and a cooling system are ongoing. The paper describes the status of the project.
