Szczegóły publikacji
Opis bibliograficzny
A pixel readout chip in 40 nm CMOS process for high count rate imaging systems with minimization of charge sharing effects / P. MAJ, P. GRYBOŚ, R. SZCZYGIEŁ, P. KMON, A. DROZD, G. Deptuch // W: 2013 IEEE NSS/MIC [Dokument elektroniczny] : Nuclear Science Symposium & Medical Imaging Conference : October 27 – November 2, Seoul, Korea / guest ed. Yong Choi ; Institute of Electrical and Electronics Engineers. — Wersja do Windows. — Dane tekstowe. — [Piscataway : IEEE], cop. 2013. — 1 dysk optyczny. — e-ISBN: 978-1-4799-3423-2. — S. [1–5]. — Wymagania systemowe: Adobe Reader ; napęd CD-ROM. — Bibliogr. s. [5], Abstr. — W bazie Web of Science wersja: ISBN 978-1-4799-0534-8. — G. Deptuch – afiliacja: Fermi National Accelerator Laboratory, USA
Autorzy (6)
Dane bibliometryczne
| ID BaDAP | 81324 |
|---|---|
| Data dodania do BaDAP | 2014-05-14 |
| DOI | 10.1109/NSSMIC.2013.6829433 |
| Rok publikacji | 2013 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Konferencja | 60th IEEE Nuclear Science Symposium / Medical Imaging Conference / 20th International Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors |
Abstract
We present a prototype chip built in a 40 nm CMOS process for readout of a pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 mu m. It can operate in both: the single photon counting (SPC) mode and the C8P1 mode. In the SPC mode using the high gain setting the measured ENC is 84 e(-) rms (for the peaking time of 48 ns), the gain is 79.7 mu V/e(-), while the effective offset spread is 24 e(-) rms. In the C8P1 mode, the chip reconstructs full charge deposited in the detector, despite the charge sharing, and it points to a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.
