Szczegóły publikacji
Opis bibliograficzny
Hardware-efficient low-power image processing system for wireless capsule endoscopy / Paweł TURCZA, Mariusz Duplaga // IEEE Journal of Biomedical and Health Informatics ; ISSN 2168-2194. — Tytuł poprz.: IEEE Transactions on Information Technology in Biomedicine ; ISSN: 1089-7771. — 2013 — vol. 17 no. 6, s. 1046–1056. — Bibliogr. s. 1055–1056, Abstr. — Publikacja dostępna online od: 2013-06-04
Autorzy (2)
- AGHTurcza Paweł
- Duplaga Mariusz
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 79242 |
|---|---|
| Data dodania do BaDAP | 2014-01-24 |
| Tekst źródłowy | URL |
| DOI | 10.1109/JBHI.2013.2266101 |
| Rok publikacji | 2013 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | IEEE Journal of Biomedical and Health Informatics |
Abstract
This paper presents the design of a hardware-efficient, low-power image processing system for next-generation wireless endoscopy. The presented system is composed of a custom CMOS image sensor, a dedicated image compressor, a forward error correction (FEC) encoder protecting radio transmitted data against random and burst errors, a radio data transmitter, and a controller supervising all operations of the system. The most significant part of the system is the image compressor. It is based on an integer version of a discrete cosine transform and a novel, low complexity yet efficient, entropy encoder making use of an adaptive Golomb-Rice algorithm instead of Huffman tables. The novel hardware-efficient architecture designed for the presented system enables on-the-fly compression of the acquired image. Instant compression, together with elimination of the necessity of retransmitting erroneously received data by their prior FEC encoding, significantly reduces the size of the required memory in comparison to previous systems. The presented system was prototyped in a single, low-power, 65-nm field programmable gate arrays (FPGA) chip. Its power consumption is low and comparable to other application-specific-integrated-circuits-based systems, despite FPGA-based implementation.
