Szczegóły publikacji
Opis bibliograficzny
Low noise 64-channel ASIC for AC and DC coupled strip detectors / Paweł GRYBOŚ, Maciej KACHEL, Piotr KMON, Robert SZCZYGIEŁ, Takeyoshi Taguchi // IEEE Transactions on Nuclear Science ; ISSN 0018-9499 . — 2011 — vol. 58 no. 1, s. 187–193. — Bibliogr. s. 192–193, Abstr.
Autorzy (5)
Dane bibliometryczne
| ID BaDAP | 58144 |
|---|---|
| Data dodania do BaDAP | 2011-03-15 |
| Tekst źródłowy | URL |
| DOI | 10.1109/TNS.2010.2099132 |
| Rok publikacji | 2011 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | IEEE Transactions on Nuclear Science |
Abstract
A 64-channel ASIC (SXDR64) aimed to work with both AC and DC coupled detectors (Si, CdTe, GaAs), in a single photon counting mode with an energy window has been developed. Every channel of the ASIC consists of a charge sensitive amplifier, a pole-zero cancellation circuit, a 4th order shaper with programmable gain from 14 μV/e- to 50 μV/e- and peaking time from 115 ns to 380 ns, a base-line restorer, two independent discriminators, and two 20-bit counters. Control and readout of the chip are done using on-chip LVDS drivers/receivers. The ASIC can work with input leakage currents in the range from -10 nA up to 7 nA. The ENC obtained with an AC-coupled Si detector is 120 e- for a peaking time Tp=115 ns and Cdet=1.2 pF. With a DC-coupled CdTe detector, the ENC is 210 e-rms for a peaking time Tp=380 ns and C det=2 pF and the leakage current Idleak=0.15 nA. The implemented trim DACs at the discriminator inputs allows to minimize the effective threshold spread to 8 e-rms (at one sigma level). The ASIC is designed in a CMOS 0.35 μm technology and its total area is 4800 × 5000 μm2.
