Szczegóły publikacji
Opis bibliograficzny
Four-quadrant analog multiplier based on CMOS inverters / Witold MACHOWSKI, Stanisław KUTA, Jacek JASIELSKI // Analog Integrated Circuits and Signal Processing ; ISSN 0925-1030 . — 2008 — vol. 55 iss. 3, s. 249–259. — Bibliogr. s. 258, Abstr. — Publikacja dostępna online od: 2008-03-22
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 42132 |
|---|---|
| Data dodania do BaDAP | 2008-12-15 |
| Tekst źródłowy | URL |
| DOI | 10.1007/s10470-008-9158-9 |
| Rok publikacji | 2008 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | Analog Integrated Circuits and Signal Processing |
Abstract
In the article a new implementation of four-quadrant analog multiplier in CMOS technology is proposed. The circuit is based exclusively on CMOS inverters (or similar two-transistor blocks) and operates using quarter square technique. The outstanding feature of the circuit is an extreme suitability for low voltage operation and full compatibility with digital CMOS, since there are only two transistors stacked-up between supply rails. Thus the supplying voltage of this circuit class is the lowest possible one for any particular CMOS technology. The operation principle based on symbolic analysis with simple square model has been fully confirmed by simulations with BSIM3v3 models provided by different silicon foundries and verified experimentally using one of them.
