Szczegóły publikacji
Opis bibliograficzny
Noise optimization of charge amplifier with MOS input transistor working in moderate inversion region / P. GRYBOŚ, M. IDZIK // W: IEEE 2005 Nuclear Science Symposium [Dokument elektroniczny] : conference record : October 23–29, 2005, Puerto Rico / guest ed. Bo Yu ; IEEE, NPSS Nuclear & Plasma Sciences Society. — Wersja do Windows. — Dane tekstowe. — [Piscataway] : IEEE, 2005. — 1 dysk optyczny. — ISBN: 0-7803-9222-1. — S. 960–964, N18-4. — Wymagania systemowe: Adobe Reader ; napęd CD. — Bibliogr. s. 964, Abstr.
Autorzy (2)
Dane bibliometryczne
| ID BaDAP | 34591 |
|---|---|
| Data dodania do BaDAP | 2007-10-08 |
| Rok publikacji | 2005 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
Abstract
The noise of a fast charge sensitive amplifier (CSA) with an input MOS transistor working in moderate inversion region is discussed. The MOS transistor operation in moderate inversion region becomes especially important in multichannel readout systems, where limited power dissipation is required. The ENC of a CSA followed by a fast shaper is usually dominated by the thermal noise of the input MOS transistor. We perform the noise minimization of such CSA, searching for an optimum input transistor width. The analysis are done using a simplified EKV model and are compared to HSPICE simulations with BSIM3v3 model. We consider several CMOS technology generations with minimum transistor gate length ranging from 0.13 mu m to 0.8 mu m. We study the sensitivity of ENC to the input transistor width and propose a simple formula to estimate the optimum. transistor width, which is valid in a wide range of the input transistor current density.
