Szczegóły publikacji
Opis bibliograficzny
FPGA-based hardware architecture for contrast maximization in event-based vision / Michał Filipkowski, Marcin KOWALCZYK, Tomasz KRYJAK // W: Applied Reconfigurable Computing : architectures, tools, and applications : 22nd international symposium, ARC 2026 : Cagliari, Sardinia, Italy, April 8–10, 2026 : proceedings / eds. Gianluca Leone, [et al.]. — Cham : Springer, cop. 2026. — ( Lecture Notes in Computer Science ; ISSN 0302-9743 ; LNCS 16514 ). — ISBN: 978-3-032-29364-0; e-ISBN: 978-3-032-29365-7. — S. 309–325. — Bibliogr., Abstr. — Publikacja dostępna online od: 2026-06-30
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 169140 |
|---|---|
| Data dodania do BaDAP | 2026-09-03 |
| DOI | 10.1007/978-3-032-29365-7_19 |
| Rok publikacji | 2026 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Springer |
| Czasopismo/seria | Lecture Notes in Computer Science |
Abstract
This paper presents a hardware architecture that implements the Contrast Maximization (CM) algorithm on Field-Programmable Gate Array (FPGA) resources for event-based vision systems. CM estimates motion parameters by maximizing the contrast of an Image of Warped Events (IWE) reconstructed from asynchronous event streams. Event-based vision sensors generate sparse, high-temporal-resolution data with low spatial redundancy, making them well-suited for hardware processing. The deterministic and massively parallel nature of FPGA devices is leveraged to design a deeply pipelined architecture that delivers high-throughput, energy-efficient processing suitable for real-time embedded applications. This paper describes the hardware modules responsible for event warping, contrast computation, and iterative optimization, discusses key implementation decisions, and presents the hardware-aware optimization method used in the design. Experimental results demonstrate substantial speed and efficiency improvements over CPU-based implementations. The acceleration factor depends on the number of input events and the region of interest (ROI) resolution, ranging from 16x to 20x across the evaluated settings. To the best of our knowledge, at the time of writing, this is the first hardware architecture that accelerates the CM algorithm in FPGA hardware. Performance is evaluated in terms of processing speed, energy efficiency, and hardware resource utilization. The proposed design is validated using an event-based object tracking example application. The results confirm that the proposed architecture provides a solid foundation for real-time motion estimation in high-speed, low-power embedded systems.
