Szczegóły publikacji
Opis bibliograficzny
Analysis of surface code algorithms on quantum hardware using the Qrisp framework / Jan Krzyszkowski, Marcin NIEMIEC // Electronics [Dokument elektroniczny]. — Czasopismo elektroniczne ; ISSN 2079-9292 . — 2025 — vol. 14 iss. 23 art. no. 4707, s. 1–23. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 22–23, Abstr. — Publikacja dostępna online od: 2025-11-29. — M. Niemiec - dod. afiliacja: Klaipeda University, Lithuania
Autorzy (2)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 164933 |
|---|---|
| Data dodania do BaDAP | 2025-12-13 |
| Tekst źródłowy | URL |
| DOI | 10.3390/electronics14234707 |
| Rok publikacji | 2025 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | Electronics |
Abstract
The pursuit of scalable quantum computing is intrinsically limited by qubit decoherence, making robust quantum error correction (QEC) techniques crucial. As a leading solution, the topological surface code offers inherent protection against local noise. This study presents the first comprehensive implementation and quantitative characterization of a full surface code pipeline, which includes encompassing lattice construction, multi-round syndrome extraction, and MWPM decoding, using the high-level Qrisp programming framework. The entire pipeline was executed on IQM superconducting quantum processors to provide an empirical assessment under current noisy intermediate-scale quantum (NISQ) conditions. Our experimental data definitively show that the system operates significantly below the fault-tolerance threshold. Crucially, a quantitative resource analysis isolates and establishes the lack of native qubit reset on the hardware as the dominant architectural bottleneck. This constraint forces the physical qubit count to scale as 𝑑2+(𝑑2−1)𝑇, effectively preventing scaling to larger code distances (d) and execution times (T) on current devices. The work confirms Qrisp’s capability to support advanced QEC protocols, demonstrating that high-level abstraction can reduce implementation complexity by simplifying scheduling and mapping, thereby facilitating deeper experimental analysis of hardware limitations.
