Szczegóły publikacji
Opis bibliograficzny
High-definition event frame generation using SoC FPGA devices / Krzysztof BŁACHUT, Tomasz KRYJAK // W: SPA 2023 : Signal Processing Algorithms, Architectures, Arrangements, and Applications : Poznan, 20th - 22nd September 2023 / IEEE The Institute of Electrical and Electronics Engineers Inc., [etc.]. — [Piscataway] : IEEE, [2023]. — (Signal Processing Algorithms, Architectures, Arrangements, and Applications Conference Proceedings ; ISSN 2326-0262). — ISBN: 979-8-3503-0498-5. — S. 106-111. — Bibliogr. s. 111, Abstr.
Autorzy (2)
Dane bibliometryczne
| ID BaDAP | 150127 |
|---|---|
| Data dodania do BaDAP | 2023-12-18 |
| Tekst źródłowy | URL |
| DOI | 10.23919/SPA59660.2023.10274447 |
| Rok publikacji | 2023 |
| Typ publikacji | materiały konferencyjne (aut.) |
| Otwarty dostęp |  |
| Wydawca | Institute of Electrical and Electronics Engineers (IEEE) |
| Czasopismo/seria | Signal Processing Algorithms, Architectures, Arrangements, and Applications Conference Proceedings |
Abstract
In this paper we have addressed the implementation of the accumulation and projection of high-resolution event data stream (HD – 1280×720 pixels) onto the image plane in FPGA devices. The results confirm the feasibility of this approach, but there are a number of challenges, limitations and trade-offs to be considered. The required hardware resources of selected data representations, such as binary frame, event frame, exponentially decaying time surface and event frequency, were compared with those available on several popular platforms from AMD Xilinx. The resulting event frames can be used for typical vision algorithms, such as object classification and detection, using both classical and deep neural network methods.