Szczegóły publikacji
Opis bibliograficzny
Low-power low-area near-lossless image compressor for wireless capsule endoscopy / Paweł TURCZA, Mariusz Duplaga // Circuits, Systems, and Signal Processing ; ISSN 0278-081X. — 2023 — vol. 42 iss. 2, s. 683–704. — Bibliogr. s. 701–704, Abstr. — Publikacja dostępna online od: 2022-08-27
Autorzy (2)
- AGHTurcza Paweł
- Duplaga Mariusz
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 145422 |
|---|---|
| Data dodania do BaDAP | 2023-03-14 |
| Tekst źródłowy | URL |
| DOI | 10.1007/s00034-022-02149-6 |
| Rok publikacji | 2023 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | Circuits, Systems, and Signal Processing |
Abstract
The paper presents the concept of a low-power, low-area, near-lossless image compressor for resource-constrained devices such as wireless capsule endoscopy (WCE). The compressor directly processes the raw data from the Bayer Color Filter Array (CFA) imager to avoid the high cost of color interpolation. To improve the efficiency of the compressor in terms of energy consumption, silicon area and compression ratio, the main part of the compressor, i.e., the entropy encoder, uses the existing correlations between the color components of a captured CFA image. The proposed image compressor requires only 12.4% of the memory needed by other high-quality CFA compressors based on the JPEG-LS standard. Despite this significant reduction in memory size, the proposed image compressor outperforms other state-of-the-art coding schemes on capsule endoscopy images. At the same time, it offers only slightly lower performance on standard test images. The proposed image compressor has been implemented as an intellectual property (IP) core using two different low-cost CMOS processes. The design, implemented in UMC 180 nm CMOS process, requires a very low silicon area (534 × 426 μ m2) and consumes very low energy (22 μ J per a single 512 × 512 image frame). Even higher energy efficiency (12 μ J per the same image frame) has the IP core implemented in the TSMC 130 nm CMOS process. Both of the selected technologies are low-cost and well-suited to implement a radio frequency transmitter and a low-power successive approximation register analog-to-digital converter in addition to the compressor to provide a cost-effective System on Chip for resource-constrained devices like WCE or wireless camera sensor network.
