Szczegóły publikacji
Opis bibliograficzny
An efficient real-time FPGA-based ORB feature extraction for an UHD video stream for embedded visual SLAM / Mateusz WĄSALA, Hubert SZOLC, Tomasz KRYJAK // Electronics [Dokument elektroniczny]. — Czasopismo elektroniczne ; ISSN 2079-9292. — 2022 — vol. 11 iss. 14 art. no. 2259, s. 1-20. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 19-20, Abstr. — Publikacja dostępna online od: 2022-07-20
Autorzy (3)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 141501 |
|---|---|
| Data dodania do BaDAP | 2022-08-31 |
| Tekst źródłowy | URL |
| DOI | 10.3390/electronics11142259 |
| Rok publikacji | 2022 |
| Typ publikacji | artykuł w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | Electronics |
Abstract
The detection and description of feature points are important components of many computer vision systems. For example, in the field of autonomous unmanned aerial vehicles (UAV), these methods form the basis of so-called Visual Odometry (VO) and Simultaneous Localisation and Mapping (SLAM) algorithms. In this paper, we present a hardware feature points detection system able to process a 4K video stream in real-time. We use the ORB algorithm—Oriented FAST (Features from Accelerated Segment Test) and Rotated BRIEF (Binary Robust Independent Elementary Features)—to detect and describe feature points in the images. We make numerous modifications to the original ORB algorithm (among others, we use the RS-BRIEF instead of classic R-BRIEF) to adapt it to the high video resolution, make it computationally efficient, reduce the resource utilisation and achieve lower power consumption. Our hardware implementation supports a 4 ppc (pixels per clock) format (with simple adaptation to 2 ppc, 8 ppc, and more) and real-time processing of a 4K video stream (UHD—Ultra High Definition, 3840×2160 pixels) @ 60 frames per second (150 MHz clock). We verify our system using simulations in the Vivado IDE and implement it in hardware on the ZCU 104 evaluation board with the AMD Xilinx Zynq UltraScale+ MPSoC device. The proposed design consumes only 5 watts.
