Szczegóły publikacji
Opis bibliograficzny
A 38.6-fJ/conv.-step inverter-based continuous-time bandpass $\Delta\Sigma$ ADC in 28 nm using asynchronous SAR quantizer / Hanie Ghaedrahmati, Jianjun Zhou, Robert Bogdan STASZEWSKI // IEEE Transactions on Circuits and Systems. II, Express Briefs ; ISSN 1549-7747. — 2021 — vol. 68 no. 9, s. 3113–3117. — Bibliogr. s. 3117, Abstr. — Publikacja dostępna online od: 2021-06-16. — R. B. Staszewski - pierwsza afiliacja: University College Dublin, Ireland. — 4th International Symposium on Integrated Circuits and Systems (ISICAS) : December 9th-11th, 2021 : hybrid way
Autorzy (3)
- Ghaedrahmati Hanie
- Zhou Jianjun
- AGHStaszewski Bogdan
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 136286 |
|---|---|
| Data dodania do BaDAP | 2021-09-22 |
| Tekst źródłowy | URL |
| DOI | 10.1109/TCSII.2021.3089831 |
| Rok publikacji | 2021 |
| Typ publikacji | referat w czasopiśmie |
| Otwarty dostęp |  |
| Creative Commons | |
| Czasopismo/seria | IEEE Transactions on Circuits and Systems, II, Express Briefs |
Abstract
We propose a self-biased inverter-based amplifier for realizing a high-speed low-power second-order single-loop continuous-time bandpass delta-sigma modulator (CT-BP-Delta Sigma M). The design is amenable to nanoscale CMOS and exploits a single self-biased pseudo-differential inverter with a positive feedback to replace conventional op-amps used in an integrator configuration. The modulator also uses a 5-bit asynchronous successive approximation register (ASAR) quantizer. With a 30 MHz bandwidth at 400 MS/s sampling rate and 100 MHz intermediate frequency (IF), the modulator achieves 61 dB dynamic range (DR) and 58 dB SNDR while consuming 2.5 mW from a 1V supply. The core area in 28 nm LP CMOS is 0.04 mm(2). A 38.6 fJ/conv.-step figure of merit is achieved.
