Szczegóły publikacji
Opis bibliograficzny
Simulation approach to charge sharing compensation algorithms with experimental cross-check / A. KRZYŻANOWSKA, G. DEPTUCH, P. MAJ, P. GRYBOŚ, R. SZCZYGIEŁ // Journal of Instrumentation [Dokument elektroniczny]. — Czasopismo elektroniczne ; ISSN 1748-0221. — 2017 — vol. 12, art. no. C03071, s. [3], 1–9. — Wymagania systemowe: Adobe Reader. — Bibliogr. s. 8–9, Abstr. — Publikacja dostępna online od: 2017-03-20. — G. Deptuch - dod. afiliacja: Fermilab PPD/EED, Batavia, U. S. A. — 18th International Workshop on Radiation Imaging Detectors : 3–7 July 2016, Barcelona, Spain
Autorzy (5)
Słowa kluczowe
Dane bibliometryczne
| ID BaDAP | 104943 |
|---|---|
| Data dodania do BaDAP | 2017-05-06 |
| Tekst źródłowy | URL |
| DOI | 10.1088/1748-0221/12/03/C03071 |
| Rok publikacji | 2017 |
| Typ publikacji | referat w czasopiśmie |
| Otwarty dostęp |  |
| Czasopismo/seria | Journal of Instrumentation |
Abstract
Hybrid pixel detectors for X-ray imaging, working in a single photon counting mode, find applications in a variety of fields, such as medical imaging, material science or industry. However, charge sharing, which occurs when a photon hits a detector in the area between two or four pixels, becomes more significant with decreasing pixel size. If the charge generated when a photon interacts with a detector is collected by more than one pixel, the photon energy and the event position may be improperly detected. Therefore, algorithms for minimization of the impact of charge sharing on a pixel detector for X-ray detection need to be implemented. Firstly, such algorithms must be assessed on a simulation level. The goal is to implement the simulations in such a way that the simulation accuracy and simulation time are optimized. A model should be flexible enough so that it can be quickly adapted for other uses. We propose behavioral models implemented in the Cadence® Virtuoso® environment. This is a solution that enables fast validation of the system at the higher level of abstraction allowing deep verification. A readout channel of a chip is represented using parameterized behavioral blocks of different functionality, such as, a charge sensitive amplifier, shapers, discriminators, comparators. The inter-pixel connections are taken into account. This approach enables top-down design and optimization of parameters. The model was implemented in particular to test the C8P1 algorithm used in the Chase Jr. chip, however, due to its modular implementation, it can be easily adjusted to further test of the algorithms. The simulation approach is described and the simulation results are presented together with the experimental data obtained during synchrotron measurements for the Chase Jr. chip with the C8P1 algorithm implemented.
